In a distributed processor control unit, a main processor supervises separate controls or controllers provided for each of the different sectors of the machines, e.g., input/output controllers. In such an environment, error detection and subsequent problem determination is complicated. The system requires means to identify any errors that occur and then to interrupt the working of the main processor while the error is evaluated and, if necessary, corrected. If more than one error occurs in any particular time period or if, during the evaluation of one error, a second error occurs, then means have to be provided to ensure that the occurrence of this second error does not influence the evaluation of the first error. In addition, it is desirable that a record is kept of the occurrence of the second error such that it can be evaluated after the main processor has completed its work on the first error. Some errors are of such significance that they cannot be corrected by the processor and means have to be provided for isolating these faults such that their repeated occurrence does not continually interrupt the functioning of the main processor.
In current systems where such error detection and fault isolation is implemented, each logic chip has an error reporting register and an associated error mask register, both of which can be read and/or written by the error handling mechanism. A mask register is used either to temporarily disable specific errors so as to allow other errors to be reported, or to permanently disable a specific interrupt in the case of defective error detection circuitry. Examples of such systems are shown in Research Disclosure No. 25236, titled "Priority Status Recording with Mask Capability", published on Apr. 10, 1985, IBM Technical Disclosure Bulletin, titled "Primary Error Detection System for I/O Apparatus", Vol. 30, No. 1, June 1987, pp 379-380 and in U.S. Pat. No. 4,932,028 titled "Error Log System for Self-Testing in Very Large Scale Integrated Circuit (VLSI) Units", issued Jun. 5, 1990 to H. Katircioglu, et al.
FIG. 1 shows a simplified view of a current approach for error logic using mask registers. For every error capture latch 20, 22, there is an associated mask latch 30, 32 which can be used in conjunction with AND gate 40, 42 to block the error from generating an interrupt in the interrupt latch 50 which is controlled through OR gate 45. To set and reset each mask latch 30, 32, control logic 10, 12 is needed to decode control commands from the error handling mechanism. In applications where there are numerous error logging elements (error capture latches), the hardware overhead for implementing the mask logic is certainly substantial. The logic gates required occupy a lot of space on the chip and are comparatively slow and inflexible.